1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and to a method of programming. More specifically, the present invention relates to a semiconductor integrated circuit device having electrically erasable and programmable non-volatile memory and a method of programming therefor.
2. Description of the Background Art
An electrically erasable and programmable flash memory has been known as one of non-volatile semiconductor memory devices. A DINOR (Divided bit-line NOR) type flash memory will be described in the following as an example of the non-volatile semiconductor memory devices.
Referring to FIG. 9, a memory block #1 of a conventional flash memory includes a plurality of memory cells M. The plurality of memory cells M are divided into a plurality of groups by select gate portions SG (SG1, . . . , SG4). Though not shown, the conventional flash memory may includes a plurality of memory blocks #2 to #n each having the same structure as memory block #1.
Configuration of the plurality of memory cells M divided into groups by the select gate portions SG will be described in the following.
The plurality of memory cells M are arranged in a matrix. A plurality of memory cells arranged in the row direction are connected to corresponding word lines WL (WL1, . . . , WLm), and a plurality of memory cells arranged in the column direction are connected to corresponding sub bit lines SBL (SBL1, . . . , SBLn), respectively. Each sub bit line SBL is connected to a main bit line MBL (MBL1, . . . , MBLn) through a transistor t0 constituting the select gate portion SG1.
Relation between the memory cells M divided into groups by select gate portion SG1 and the memory cells M divided into groups by select gate portion SG2, SG3 or SG4 will be described.
The main bit line MBL is common to respective groups. Word lines WL (WL1, . . . WLm) are common to the groups divided by select gate portion SG1 and groups divided by select gate portion SG2 (similarly, these are common to groups divided by select gate portions SG3 and SG4). These word lines WL (WL1, . . . , WLm) are connected to a common word line driver line WLD (WLD1, . . . , WLDm).
For simplicity, the select gate portion will be denoted by SG, word line by WL, main bit line by MBL, sub bit line by SBL and word line driver line by WLD.
When any of the word line driver lines WLDs attains to the H (high) level, a corresponding word line WL is set to a selected state.
A collection of memory cells M within a group selected by any one of the selected gate portions (SG1 to SG4) and connected to that word line which is selected by the word line driver line WLD is referred to as a page.
By selecting a page and by setting one main bit line MBL to the selected state, a memory cell M to which writing is to be done, is selected. Programming of a memory cell M belonging to the selected page is referred to as page programming.
Writing of information to the memory cells M constituting the conventional flash memory will be described with reference to FIG. 10. Writing to a memory cell M is performed by changing threshold voltage thereof.
Referring to the threshold voltage distribution of the memory cell M shown in FIG. 10, a state in which the threshold voltage is within the range of depletion verify voltage VDV to program verify voltage VPV is referred to as a programmed state or a state storing data "0". A state in which the threshold voltage is higher than the erase verify voltage VEV is referred to as an erased state or a state storing data "1". The state in which the threshold voltage is lower than the depletion verify voltage VDV is referred to as an over programming state (hereinafter, the memory cell M in this state will be referred to as an over bit cell OPbit).
When memory cell M is to be set to the programmed state, the threshold voltage is controlled so that it is within the range of VDV voltage to VPV voltage. When memory cell M is to be set to the erased state, the threshold voltage is controlled such that it attains higher than the VEV voltage.
In the following, for simplicity, the memory cell M AS selected for programming will be referred to as a selected cell M0 and other memory cells M will be referred to as non-selected cells M1.
The method of programming selected cell M0 and disturbance associated with programming will be described with reference to FIG. 11.
Though basic configuration of non-selected cell M1 is not described, it is the same as selected cell M0 except the condition of voltage application.
Referring to FIG. 11, selected cell M0 includes a control gate electrode layer 90, a floating gate layer 91, a drain region 92 and a source region 93. Drain and source regions 92 and 93 are formed spaced by a prescribed distance in a substrate 94. Control gate electrode 90 is connected in the row direction, to word line WL. Drain region 92 is connected to main bit line MBL through select gate portion SG. Source region 93 is connected to a source line SL.
At the time of programming, a negative high voltage is input to control gate electrode 90 through the word line WL to which selected cell M0 is connected. A positive high voltage from the main bit line MBL is applied through select gate portion SG to drain region 92. Source region 93 is at a floating state. Accordingly, electrons existing in floating gate electrode layer 91 are drawn by tunneling phenomenon, to the drain region 92. As a result, a state of low threshold voltage (data "0") is attained.
It is known that when a voltage is applied to selected cell M0, the data stored in non-selected cell M1 is disturbed. Here, disturbance means that the voltage applied to non-selected cell M1 during writing, erasure or reading of selected cell M0 fluctuates, resulting in fluctuation of the threshold voltage of non-selected cell M1.
Gate disturbance experienced at a non-selected cell M1 will be described with reference to FIG. 12.
Referring to FIG. 12, drain region 92 and source region 93 of non-selected cell M1 (data "1") connected to the same word line WL as selected cell M0 are at the floating state.. To control gate electrode layer 90, a negative high voltage is applied through word line WL, as in selected cell M0.
Under this voltage application condition, it is possible that electrons undesirably move to substrate 94 from floating gate electrode layer 91 of none-selected cell M1. This means that non-selected cell M1 makes a transition from a state of high threshold voltage (data "1") to a state of low threshold voltage. Disturbance experienced by non-selected cell M1 under such voltage application condition is specifically referred to as gate disturbance.
In view of the foregoing, in an electrically erasable and programmable memory cell M, it is important to solve the problem of disturbance experienced in the non-selected cell M1 to ensure high reliability.
The conventional flash memory further experiences the problem that immunity to gate disturbance deteriorate as the source potential VS increases by the gate disturbance.
Relation between the source potential VS and immunity to gate disturbance will be described with reference to FIGS. 13, 14 and 15.
Referring to FIGS. 13 and 14, every time a program pulse is applied (time T1 to T6), drain potential VD of selected cell M0 changes and source potential VS rises.
When source potential VS increases, the electric field between control gate electrode layer 90 and source region 93 (FIG. 12) intensifies, and as a result, it becomes highly possible that gate disturbance is accelerated.
Referring to FIG. 15, when source potential VS rises (time T1 to T3) and an overbit cell OPbit results (time T4), and further the program pulse is applied, the source potential VS exceeds the upper limit Vgd.max of tolerable range of the gate disturbance immunity (time T5 to T6) because of the leak current flowing through overbit cell OPbit.
In order to solve this problem, source potential VS may be clamped when it exceeds a certain level. However, the method of simply clamping source potential VS still has the following problem.
More specifically, when the source potential VS is clamped, the source potential VS never exceeds the upper limit Vgd.max of the tolerable range of gate disturbance immunity. However, referring to FIG. 16, it means that a voltage at the clamp level Vclamp is continuously applied (T4 to T6) to the source line SL until programming of the selected cell M0 connected to the sub bit line SBL having overbit cell OPbit connected thereto is completed. This causes increase in gate disturbance stress, which may possibly deteriorate immunity to gate disturbance.
This may possibly prevented by setting lower the clamp potential Vclamp. However, if clamp potential Vclamp is set low, load current flowing through a circuit applying a high voltage to drain region 9,2 (FIG. 11) of selected cell M0 increases, causing another problem that a desired high voltage cannot be generated.
In a conventional program sequence P1, an operation of erasing and writing all over again is performed on the generated overbit cell, so as to recover the threshold voltage and to prevent deterioration of gate disturbance immunity. However, the conventional program sequence P1 suffers from the following problem.
The conventional program sequence P1 (for a page program) will be described with reference to FIG. 17.
The conventional program sequence P1 shown in FIG. 17 includes Sequence 1 (steps S1 to S3) and Sequence 2 (steps S4 to S6).
In steps S1, before applying the program pulse to selected cell M0, program verifying operation is performed. In steps S2, the program pulse is applied to the selected cell M0. In step S3, program verifying operation is performed in selected cell M0. Sequence 1 is performed on all the memory cells M in the selected page.
In step S4, depletion verifying operation is performed only on the selected page, to detect any overbit cell OPbit which is in the over programmed state. When there is not an overbit cell OPbit, programming of the selected page is completed.
When there is an overbit cell Opbit, the operation of erasing is performed on overbit cell OPbit in step S5. More specifically, channel hot electrons are injected to the overbit cell OPbit. Consequently, the threshold voltage is set higher than depletion verify voltage VDV. In steps S6, Sequence 1 is performed, so that the threshold voltage is made lower than the program verify voltage VPV.
However, in the conventional DINOR type flash memory, gate disturbance is possible not only in the non-selected cells M1 in the selected page but also non-selected cells M1 connected to the same word line WL of different groups.
Therefore, in the conventional flash memory, when the conventional program sequence is performed, overbit cells OPbit existing in pages other than the selected page are left as they are, which may deteriorate immunity to gate disturbance.